100336

40% power reduction of the 100136
2000V ESD protection
Pin/function compatible with 100136
Voltage compensated operating range = −4.2V to −5.7V
Standard Microcircuit Drawing (SMD) 5962-9230601

Storage Temperature (TSTG) −65°C to +150°C
Maximum Junction Temperature (TJ) +150°C
VEE Pin Potential to Ground Pin −7.0V to +0.5V
Input Voltage (DC) VEE to +0.5V
Output Current (DC Output HIGH)−50 mA
ESD (Note 3)2000V

The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (S_n) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP#, CET#) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET#) input also doubles as a Serial Data (D₀) input for shift-up operation. For shift-down operation, D₃ is the Serial Data input. In counting operations the Terminal Count (TC#) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC# output repeats the Q₃ output. The dual nature of this TC#/Q₃ output and the D₀/CET# input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (P_n) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flip-flops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 k Ohm pull-down resistors.

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