100331

35% power reduction of the 100131
2000V ESD protection
Pin/function compatible with 100131
Voltage compensated operating range = −4.2V to −5.7V
Available to industrial grade temperature range
Available to Standard Microcircuit Drawing (SMD) 5962-9153601

Storage Temperature (T_STG) −65°C to +150°C
Maximum Junction Temperature (T_J)+150°C
Pin Potential to Ground Pin (V_EE) −7.0V to +0.5V
Input Voltage (DC) V_EE to +0.5V
Output Current
(DC Output HIGH) −50 mA
ESD (Note 2) 2000V

The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 k pull-down resistors.