Published:2011/6/17 19:51:00 Author:Borg | Keyword: square wave doubler | From:SeekIC
In the figure is the square wave doubler. In the circuit, gate G1 is the phaser inverter, the input signal crosses G1 and then in imposed on the input terminal of G2. When the voltage on the two terminals of C1 reaches the G2 threshold voltage, the output of G2 becomes logic 0 , at the moment, C2 discharges with the help of G2. When the input signal comes back to logic 1 , C1 is discharging with the help of G1 and C2 is charged by R2. When the voltage on the two terminals of C2 reaches the threshold voltage, the output of G3 becomes logic 0 . The NAND of G5, G6, 67 and G8 composes the OR gate.
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