Published:2011/6/17 22:14:00 Author:Borg | Keyword: frequency splitter | From:SeekIC
In the figure is the odd-even frequency splitter circuit. This circuit can engage in 2~32 (including odd and even) times of splitting. The counting input of the synchronized counter SN74193 is provided by the output 1Y of the multiplexer SN74153, the borrow output of the counter can not only drive the trigger SN7476, but also it's the deposit input pulse of SN74193. The 5-bit binary numbers are imposed on D0, D1, D3 and D4 input terminals, which decides the splitting constant(2~32), and D0 is the lowest bit. When D0=0, the outputting pulse phase of the multiplexer is determined according to the trigger state.
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