Published:2011/6/26 20:35:00 Author:Borg | Keyword: digital frequency divider | From:SeekIC
In the figure is the digital frequency divider, which consists of 3 integrated circuits, and its dividing coefficient ranges from 1 to 9. The counter SN7490 outputs the binary-coded decimal numbers which are sent to the decoder SN7442, and the decoder outputs decimal numbers. The dividing coefficient is decided by the selector SN 74150. The output of the data selector is fed back to the reset input terminal of SN7490, i.e a pulse is output once a counting period is over, the pulse is resetting the counter SN7490 at the same time. The width of the pulse is 60ns, which is decided by the delayed transmitting time.
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