The 3-way frequency circuit of symmetric output(74LS109 and 74LS113)

Published:2011/6/17 20:25:00 Author:Borg | Keyword: 3-way frequency, symmetric output | From:SeekIC

In the figure is the 3-way frequency circuit of symmetric output. Usually, when we use common counter to odd-split the digital pulse, even the input is the symmetric signal, the output won't be the splitting frequency of 50% duty cycle, the reason is that all the internal triggers are motivated by the rising edge (or the dropping edge). To solve the problem, we can use a J and K, two JK triggers that are motivated by the clock, see as figure (a). The circuit includes two JK triggers and a RS trigger.



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