Published:2009/7/9 1:21:00 Author:May | From:SeekIC
In a basic astable timer,configuration periods t1 and t2 are not controlled independently. The lack of control make it difficult to maintain a constant period,T,if either t1 or t2 is varied.In this circuit,charge RAB and discharge RBC resistance are determined by the position of common wiper arm B of the Potentiometer so,it is possible to adjust the duty-cycle by adjusting t1 and t2 Proportionately,without changing period T.
At start-up,the voltage across G is less than the trigger level voltage (1/2 VDD),causing the timer to be triggered via pip 2,The output of the timer at m 3 Increases,turning off the discharge transistor at pin 7 and allowina Ct to charge through diode D1 and resitance RAB.When capacitor Ct charges to upper threshold voltage 2/3 VDD,the flip-flop is reset and the output at pin 3 decreases through diode D2 and resistor RBC.When the voltage at pin 2 reaches 1/3 VDD,the lower threshold or trigger level,the timer triggers.again and the cycle is repeated.In this circuit,the oscillator frequency remains fixed and the duty cycle is adjustable from less than 0.5% to greater than 99.5%.
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