DIGITAL_BURST_GENERATOR_

Published:2009/7/14 3:25:00 Author:May | From:SeekIC

Figure 1 illustrates the transmitted signal and the continuous sine wave from which it is derived. Because the HA4600 buffer has an enable/disable feature, it will pass or reject the input waveform, depending on the state of the enable pin (Fig. 2.). The input signal also is present at the input to the HFA3046 transistor array, which has been configured as a high-speed, high-gain comparator. The comparator squares up the input signal and applies it to the inputs of the two counters, X and Y. The X counter controls the buffer enable, and it determines how many cycles of the input waveform get passed to the output. The four switches SX0 through SX3 are binary-coded. Consequently, if two switches (SX0=1 cycle and SX3=2 cycles) are closed, three cycles of the input sine wave will be passed to the output. Furthermore, the input signal is connected to the Y counter, which controls the repetition rate by determining the OFF period between pulse bursts. The four switches SY0 through SY3 are binary-coded. When all of these switches are closed, the OFF period will be 16 times the period of the input waveform. With the X and Y counters set as described earlier, the repetition rate is the reciprocal of (16+3) times the period of the incoming waveform. If a longer repetition rate is desired, a flip-flop or another counter can be added in series with the output of the Y counter to extend the OFF time. R6, R7, and R8 bias the long-tailed transistor at 10 mA, which is the optimum point for speed. R5 and R6 are small enough to discharge quickly, thus preventing saturation. Configured as shown, the circuit will handle 10-MHz input signals with little degradation. The limit on frequency response is the speed of the logic and the comparator delay time. The comparator delay time can be eliminated by one-shotting out the delay.



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