256-nary counter circuit

Published:2011/6/5 10:39:00 Author:John | Keyword: 256-nary counter | From:SeekIC

In the 160-counter, when S1 = S2 = 0, the counter to keep Q, C = 0. When S1 = S2 = 1, the counter starts to count. A.Define 1# a low chip and define #2 a high chip. Use a low chip’s injection output end C as the control signal, which is carried to a high chip (C edge is used to control S1 and S2 ends of high chip rather than to trigger the CP pulse end of a high counter. The value of high counter can be controlled or kept. When the low counter counts from state 0 to 8, the C is equal to zero. The counting value of high counter S1 = S2 = 0 is got. And high counter has not been compared.



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Signal_Processing/256_nary_counter_circuit.html

Print this Page | Comments | Reading(3)