LOW_STANDBY_POWER

Published:2009/7/1 20:20:00 Author:May | From:SeekIC

Basic 555 timer circuit is combined with control logic to keep drain from 12-V supply down to 1μA during standby. Drain increases to 6 mA when input signal makes output pulse go high. Circuit can be interfaced with CMOS logic. Negative-going input pulse triggers SR flip-flop, which in turn saturates a, and applies power to 555. Simultaneously, C2 feeds trigger to trigger input pin 2 of 555, to make output pulse go high. At end of time delay determined by values of R and C, timer output goes low and transition resets flip-flop for standby operation.-K. J. Imhof, 555 One-Shot Circuit Features Low-Power Standby Mode, EDN Magazine, April 20, 1978, p 134.



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