Published:2009/6/25 1:47:00 Author:May | From:SeekIC
The detector uses three sections of an L144 and a DC4011 type CMOS NAND gate to make a very low power voltage monitor. If the input voltage, VIN, is above VHIGH or below VLOW, the output will be a logical high. If (and only if) the input is between the limits will the output be low. The 1 megohm resistors RI, R2, R3, and R4 translate the bipolar ±10V swing of the op amps to a 0 to 10V swing acceptable to the ground-referenced CM0S logic.
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