Level test circuit diagram composed of 4011 CMOS NAND gate connected as an inverter

Published:2011/5/3 4:21:00 Author:Ecco | Keyword: level test , CMOS , NAND gate, inverter | From:SeekIC

The level test circuit diagram composed of 4011 CMOS NAND gate connected as an inverter is shown as the chart. In this circuit, it can use NOT gate to instead of 4011. High level shows H, low level displays L. Since R2 ~ R4 has played the role of limiting current, the digital tube and its anode is connected directly with the positive power supply Vcc. The high, low level illuminated strokes e, f are connected to ground by R4, it may reduce the driving current.



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