LOGIC_LINE_MONITOR

Published:2009/7/7 3:57:00 Author:May | From:SeekIC

This circuit requires only one CMOS IC, which is available in a 14-pin surface-mount package. The figure shows the logic lines going to a standard 9-bit parity comparator chip. This device is conventionally used in data transmission and recording applications to provide a means of error-detection by comparing the received eight- or nine-bit words with their corresponding parity bits. If the sum of the one's in a received word is odd but the odd-par-ity bit is low, then that word is known to be in error and requires retransmission. When one of the logic lines decreases, the output of the parity comparator decreases, generating a wake-up interrupt to the microprocessor. The ninth line comes from a port on the microprocessor and is toggled to reset the output signal high again, ready for the next logic change.



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