DUTY_CYCLE_MONITOR

Published:2009/7/7 22:29:00 Author:May | From:SeekIC

The circuit monitors and displays a digital signal's duty cycle and provides accuracy as high as ±1%.Using switch S2, you can choose a frequency range of either 250 Hz to 2.5 kHz at ±1% accuracy or 2 kHz to 50 kHz at ±10% accuracy. The common-cathode display gives the signal's duty-cycle percentage.Phase-locked loop IC4 and counters IC5A and IC5B multiply the input frequency by a factor of either 10 or 100, depending on switch S2's setting. IC6A and IC6B count this multiplied frequency during the incoming signal's mark interval. IC7 and IC8 then latch this count and display it at the clock's sample rate. For example, if you select a 1% resolution, when the signal's mark period is 40% of the total period, the circuit will enable the counter comprising IC6A and IC6B for 40 counts. To obtain space-interval sampling, you can reverse the input polarity using switch 51. IC2A samples the input signal's period and enables gate IC2C and resets the counter. IC2E and IC2F form the sample-rate clock; IC3B synchronizes the clock's output with the input, so that the circuit can update latches IC7 and IC8.



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