DIVIDE_BY_ODD_NUMBER_COUNTER

Published:2009/7/10 4:55:00 Author:May | From:SeekIC

This circuit symmetrically divides an input by virtually any odd number. The circuit contains n+l/2 clocks twice to achieve the desired divisor. By selecting the proper n, which is the decoded output of the 74LS161 counter, you can obtain diisors from 3 to 31. This circuit divides by 25; you can obtain higher divisors by cascading additional LS161 counters. The counter and IC5A form the n+l/2 counter. Once the counter reaches the decoded counts, n, IC5A ticks off an additional 1/2 clock, which clears the counter and puts it in hold. Additionally, IC5A clocks IC5B, which changes the dock phasing through the X0R gate, IC1. The next edge of the input clocks IC5A, which reenables the counter to start counting for an additional n+l/2 cycles. Although the circuit has been tested at 16 MHz, a worst-case timing analysis reveals that the maxi-mum input frequency is between 7 and 8 MHz.



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