8_DIGIT_UP_DOWN_COUNTER

Published:2009/7/1 2:46:00 Author:May | From:SeekIC

This circuit shows how to cascade counters and retain correct leading zero blanking.The NAND gate etects whether a digit is active since one of the two segments a or bis active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked, the Q output of the flip flop goes high and turns on the npn transistor, thereby inhibiting leading zero blanking on the low order counter.



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Measuring_and_Test_Circuit/8_DIGIT_UP_DOWN_COUNTER.html

Print this Page | Comments | Reading(3)