FAST_SAMPLE_AND_HOLD

Published:2009/7/20 21:42:00 Author:Jessie | From:SeekIC

Strobe pulse developed from logic input of 531 opamp IC, turns on JFET Q1 to complete feedback loop to IC1, Q1, and Q2. C1 charges to voltage equal to that of input signal plus gate-to-source offset voltage of Q2. At end of strobe time, feedback loop is broken and C, holds voltage until time of next strobe pulse. Decay in output voltage between samplings is 1mV/s.- Signetics Analog Data Manual, Signetics, Sunnyvale, CA, 1977, p 643-644.



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