Published:2009/7/21 23:46:00 Author:Jessie | From:SeekIC
8-digit up/down counter using two cascaded ICM7217 28-pin DIPs. The NAND gate whether a digit is active since one of the two segments not-a or not-b is active on any unblanked number. The flip-flop is clocked by the LSB of the higher-order counter so if this digit is unblanked the Q output of the flip-flop goes high and turns on the NPN transistor, inhibiting leading zero blanking on the lower-order counter (courtesy Intersil, Inc.).
Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Electrical_Equipment_Circuit/8_digit_up_down_counter_using_two_cascaded_ICM7217_28_pin_DIPs.html
Print this Page | Comments | Reading(3)
Code: