CLOCK_WITH_REFRESH_CONTROLS

Published:2009/7/10 22:54:00 Author:May | From:SeekIC

Crystal-stabilized 1-MHz clock source such as Motorola K1100A produces complementary 5-V clock outputs required for phases 1 and 2 of MC6800 MPU and also provides interface signals required for dynamic (refresh request and refresh grant) and slow (memory ready) memories. Refresh control circuit uses MC7479 dual latch, MC7404 hex inverter, and pair of 10K pull-up resistors. If ref resh request state is low when sam pled during leading edge of phase 1, phase 1 is held high and phase 2 low for at least one full clock cycle. Refresh grant signal is high to indicate to dynamic memory system that refresh cycle exists. If memotry ready line is low when sampled on leading edge of phase 2, phase 1 is held low and phase 2 high until memory ready line is brought high by slow memory controller.All transistors are MP06842.- Microprocessor Applications Manual (Motorola Series in SolidState Electronics), McGraw-Hill, New York, NY, 1975, p 4-57-4-58.



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