90% for the maximum duty cycle gate drive circuit

Published:2011/6/9 0:33:00 Author:John | Keyword: gate drive | From:SeekIC

90% for the maximum duty cycle gate drive circuit is shown in the figure. The key of the circuit is the clamp circuit composed of capacitance coupling circuit and VD1. The secondary side output signal of pulse transformer Tl is positive. When the upper part is positive and the lower one is negative, the output signal leads to conduct VD2 and VD3 through C2. Such provides drive signals for the power MOSFET’s gate and drives it to turn on. When the secondary side output signal of T1 is negative, also known as that upper part is negative and the lower one is positive, VD2 and VD3 turn off due to the clamping action of VD1. VTl is saturated to conduct, leading the power MOS-FET gate’s charge to be rapidly discharged. As a result, on / off delay time for the power MOSFET has been reduced.



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