TRANSPARENT_LATCH

Published:2009/7/14 12:03:00 Author:May | From:SeekIC

The circuit depicted here, which yields two independent latches per chip, is rather simple and inexpensive to build (see the figure). The second buffer A2 is wired with resistor R1 in the feedback path (ignore A1 for the moment). A2 with feedback resistor R1 is a stable latch. Because of the very low input current requirements of A2, there is hardly any voltage drop across R1. As a result, the input is the same as the output, and that is fed forward through the buffer, mA1ntA1ning a stable level. When buffer A1 is enabled, the input of A2 is driven to the same level as D. Even if A2's output (Q) is at an opposite logic level, which can happen momentarily (for a gate delay) when D is opposite to Q, Al is required to sink or source current through R1. After a gate delay, this signal propagates to Q. Both sides of R1 are now at the same logic level. When the LE signal goes inactive, A1 tristates and the latch will hold the level present at D one setup time prior to LE's going inactive.



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