single-transistor phase splitter

Published:2013/5/16 1:49:00 Author:muriel | Keyword: single-transistor phase splitter | From:SeekIC

The circuit uses the inverting properties of an emitter follower with a collector load. You have to experiment for a value of R and the pot that will keep the transistor's power dissipation within limits given the V+. The output stage should be buffered by another emitter follower stage, or an op amp, etc. Note that this circuit induces some loss in the p-p value of the signal, too. It is not completely distortionless, but reasonable if you do it right. The same topology can be employed with op amps: One inverting and one non-inverting with the pot between their outputs, buffered by a third op amp.



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