Basic Circuit

74 Series digital circuit of 74LS363 octal D flip-flop(tristate)

Published:2011/7/25 3:48:00 Author:Lucas | Keyword: 74 Series , digital circuit , octal D flip-flop, tristate

Edge-triggered D flip-flop; the minimum Voh level is 3.65V; 74LS374 is similar with the circuit, but the typical minimum VOH is 2.4V. Q0 = the output level before establishing the steady-state input conditions.   (View)

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74 Series digital circuit of 74LS364 octal D flip-flop(tristate)

Published:2011/7/25 3:45:00 Author:Lucas | Keyword: 74 Series, digital circuit , octal D flip-flop, tristate

Q0 = the output level before establishing the steady-state input conditions. Edge-triggered D flip-flop; the minimum Voh level is 3.65V; 74LS374 is similar with the circuit, but the typical minimum VOH is 2.4V.   (View)

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74 Series digital circuit of 74365A/366A six buffer / bus driver(three-state)

Published:2011/8/1 1:22:00 Author:Lucas | Keyword: 74 Series , digital circuit , six buffer , bus driver, three-state

Three-state output; 365 is the in-phase output; 366 is the inverted output; G1 and G2 are the public control.   (View)

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74 Series digital circuit of 74367A/368A six buffer / bus driver

Published:2011/8/1 1:20:00 Author:Lucas | Keyword: 74 Series, digital circuit, six buffer , bus driver

Three-state output; 367 is the in-phase output; 368 is the inverted output; G1 non-controls four doors (1 ~ 4), and G2 non-controls the other two doors.   (View)

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2_W_WITH_IC

Published:2009/6/28 23:26:00 Author:May

Uses Motorola MFC9020 audio power amplifier to give maximum output of about 2 W for 16-ohm loudspeaker. Used in autopatch system for FM repeaten-R. B. Shreve, A Versatile Autopatch System for VHF FM Repeaters, Ham Radio, July 1974, p 32-38.   (View)

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74 Series digital circuit of 74LS374 octal D flip-flop(tristate)

Published:2011/7/25 3:31:00 Author:Lucas | Keyword: 74 Series , digital circuit , octal D flip-flop, tristate

Three-state output: all the load is full parallel stored; it has buffer control input; clock pulse positive edge is triggered; 74LS364 is the similar to 74LS374 but has the MOS interface, high VOH. Q0 = the output level before establishing the steady-state input conditions.   (View)

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70_dB_GAIN_WITH_15_V

Published:2009/6/28 23:24:00 Author:May

Operates from sihgle penlight qell at current drain of 0.5 mA. ldeal as self-contained unit inserted in microphone cable. Q2-Q4 form 70-dB voltage amplifier. Q5 is detector, and Q6 is emitter-follower driving AGC transistor Q1.3-dB bandwidth is about 100 Hz to 8 kHz. Full output is about 200 mVRMS, while low output terminal is 1 mVRMS.-C.Hall, Low-Voltage Audio AGO Amplifier, Ham Radio, Dec. 1973, p 32-34.   (View)

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74 Series digital circuit of 74LS385, 74F385 four serial adder / subtractor

Published:2011/8/1 1:15:00 Author:Lucas | Keyword: 74 Series , digital circuit , four serial adder , subtractor

It has buffered clock and direct clear input; 2's complement independent add/ subtract and four independent outputs are related to A and B inputs controlled by S / A console.   (View)

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LINE_DRIVER

Published:2009/6/28 23:23:00 Author:May

  (View)

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50_OHM_DRIVER

Published:2009/6/28 23:21:00 Author:May

Circuit Notes To buffer a test generator to the outside world requires an amplifier with sufficient bandwidth and power handling capability. The circuit is a very simple unity gain buffer. It has a fairly high input impedance, a 50 ohm output impedance, a wide bandwidth, and high slew rate. The circuit is simply two pairs of emitter ollowers. The base emitter voltages of Q1 and Q2 cancel out, and so do those of Q3 and Q4.The preset is used to zero out any small dc offsets due to mismatching in the transistors.   (View)

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74 Series digital circuit of 74S412 multi-mode buffer latch (tristate)

Published:2011/7/25 3:25:00 Author:Lucas | Keyword: 74 Series , digital circuit , multi-mode buffer latch , tristate

Three-state output; mode input or selecting input allows output to storage in the enabled or disabled state; the typical value of high output is 4V, which can directly drive most of the MOS circuit; it can exchange with Intel 312 or 8212 directly. Q0 = the output level before establishing the steady-state input conditions.   (View)

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74 Series digital circuit of 74LS423, 74HC423 dual retriggerable monostable multivibrator (with clearing)

Published:2011/7/25 3:39:00 Author:Lucas | Keyword: 74 Series, digital circuit , dual retriggerable , monostable multivibrator , clearing

Two oscillators have a negative trigger input A and a positive trigger input B, but each end can be used to ban on the importation; when the clearing input end is in single-pulse low level, it is enable to clear, but will not be cleared trigger. *is the unstable state.   (View)

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74 Series digital circuit of 74LS245,74F245 eight inverting buffer(three-state)/line driver

Published:2011/8/1 1:10:00 Author:Lucas | Keyword: 74 Series, digital circuit , eight inverting buffer, three-state), line driver

  (View)

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74 Series digital circuit of 74290,74LS290 decimal counter

Published:2011/7/29 1:38:00 Author:Lucas | Keyword: 74 Series , digital circuit , decimal counter

Frequency-halving and one-fifth frequency; it has zero gate and 9 inputs. Electrical performance and functionality are the same with the 7490A and 74LS90A. It just changes the lead arrangement.   (View)

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DRIVER_CIRCUITS

Published:2009/6/28 23:11:00 Author:May

Circuit NotesCM0S drivers for relays, lmps,speakers,etc, offers extremely low standby power. At Vcc = 15V, power dissipation per package is typically 750 nW when the outputs are not drawing current. Thus, the drivers can be sitting out on line (a telephone line, for example) drawing essentially zero current until activated.   (View)

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DECADE_FREQUENCY_DIVIDER

Published:2009/6/28 23:05:00 Author:May

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74 Series digital circuit of 74279,74LS279 four R-S latch

Published:2011/8/1 1:50:00 Author:Lucas | Keyword: 74 Series , digital circuit , four R-S latch

74279,74LS279, 74HC279four R-S latch Double-clamped input, totem pole output Q0 =the output level before establishing the steady-state input conditions. If the output level is stable, when the S and R simultaneously reach high level, the state can not be maintained. For the latch with two S inputs; H = two L inputs, which is high; L = one or two S inputs ,which is low.   (View)

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PIN_DIGDE_ATTENUATOR

Published:2009/6/28 22:51:00 Author:May

Designed for insertion between antenna and input of any HF receiver to improve adjacent-channel selectivity by providing attenuation ahead of mixer for entire tuning range. Hewlett-Packard 5082-3379 PIN diode has very low impedance when conducting and very high impedance when biascurrent is small. NPN transistor Q1 provides over 100 mA as current source to PIN diode. Q1 is driven by AGO circuit through JFET buffer Q3.AGC voltage is derived from top of audio gain control in receiver for rectification, with 200 mVRMS at input of opamp U1 giving maximum attenuation. Center tap of T1 (any small AF transformer) can be grounded. CR1 and CR2 are germanium diodes. Article also gives circuit of IF system using cascaded 9-MHz crystal filters to improve selectivity further and provide over all AGC control range of 70 dB.-M. Goldstein, Improved Receiver Selectivity and Gain Control, Ham Radio, Nov. 1977, p 71-73.   (View)

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74 Series digital circuit of 74276 four JK flip-flop

Published:2011/7/29 1:47:00 Author:Lucas | Keyword: 74 Series , digital circuit, four JK flip-flop

It has the negative edge trigger with lag effect, and the clock is independent, then the hysteresis is typically 200mv; typical clock input frequency is 50MHz; it has buffer output.Unsteady state. When the preset and clear goes high at the same time, the state will not be maintained. Q0 = the output level of Q before establishing the steady-state input conditions.   (View)

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ACTIVE_ANTENNA

Published:2009/6/28 22:41:00 Author:May

Uses tuned loop with relatively low a for broadband operation over one amateur band, phase-coupled by FET to 10-inch vertical sensing antenna to give unidirectional reception pattern. Loop is tuned to either 80 or 40 meters by trimmer capacitor at its base. Out.put of loop is coupled to another 3N142 FET used as source follower, to isolate output of loop from heavy loading eff ect of 50-ohm transmission line going to receiver. Performance is comparable to that of full-size quarter-wave vertical antenna on 40 meters. Battery source can be used because drain is only about 2 mA.-J. J. Schultz, An Experimental Miniature Antenna for 40 to 80 m, 73 Magazine, June 1973, p29-32.   (View)

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