VERSATILE_MONO

Published:2009/7/1 5:15:00 Author:May | From:SeekIC

Uses standard digital IC voltage levels as inputs, and can be enabled or inhibited at any time without causing output pulse. Input gate Q3-Q4 is enabled with logic 1 at point A and inhibited with logic O.Logic 1 at B starts timing cycle. Q1 is 2N3819 JFET, and all other transistors are 2N3704.-R. Tenny, Versatile One-Shop, EEE Magazine, Sept. 1970, p 89



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