The gate drive circuit with the maximum 90% duty cycle

Published:2011/7/4 22:46:00 Author:Lucas | Keyword: gate drive , maximum , 90%, duty cycle | From:SeekIC

The key of the circuit is that the capacitive coupling circuit and VD1 form the clamp circuit. The output signal of secondary side in pulse transformer Tl is positive, that means up is positive while under is negative, the output signal can make VD2 and VD3 turn off by C2 to provide drive signal for the power MOSFET gate and make it turn on; Tl secondary side output signal is negative, that means up is negative while under is positive, due to the clamping effect of VD1, VD2 and VD3 are turned off, VTl is saturated conduction, the power MOS-FET gate charges and discharges rapidly to reduce the power MOSFET on / off delay time.



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