SQUARE_WAVE_PULSE_EXTRACTOR

Published:2009/7/10 2:36:00 Author:May | From:SeekIC

This circuit traps a single positive pulse from a square-wave train. Following the rising edge of an input command, the pulse-out signal emits a replica of one positive pulse of the clock signal simultaneous with the clock signal's next rising edge. The input command signal sets the Q1 output of flip-flop IC1A. Consequently, the next rising edge of the clock signal sets the Q2 output of IC1B, which allows AND gate IC2C to pass the clock signal's next positive pulse. AND gates IC2A and IC2B prevent the generation of brief output glitches by delaying the clock signal by tD seconds (two propa-gation delays).



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