Quasi - synchronous decimal counter circuit

Published:2012/8/15 2:39:00 Author:Ecco | Keyword: Quasi - synchronous , decimal counter | From:SeekIC

The circuit is adder circuit composed of asynchronous decimal counter FJJ141 or the 7490A. All levels'data is transferred by decoding circuit. So output ends A , D are in high level only after nine pulses comes. Once two pulses arrive, they will be transferred to next preset end for carrying signal by two interconnected gates ( gate 1 and 2, or gate 1 and a corresponding NAND gate ), then the circuit realizes the decimal counting.



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