Partially_decoded_NSC800_interface

Published:2009/7/25 5:12:00 Author:Jessie | From:SeekIC

Figure 9-24 shows the ADC0816/17 connected to form a partially coded NSC800 interface. This interface is quite similar to that for the 8080-even though the timing is very different. The NSC800 multiplexes the lower 8 address bits on the data bus at the beginning of each cycle. When accessing memory, A0 through A7 must be latched out at the beginning of a read or write cyde. For I/O accessing, the NSC800 duplicates the 8-bit I/O addresses on A8 through A15 address lines. Latches are not necessary because these lines are not multiplexed. The I/O read and write strobes are taken from RD (read) and WR (write) lines and the IO/M signal. A dual 2-4 line decoder decodes A15. A14 is enabled by the read-write strobes. Tristate inverters are used to implement a decoding stmitar to that of Fig. 9-21. Double pulsing is not required because START and ALE are accessed separately. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, 1994, P. 608.



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