PSEUDORANDOM_CMOS

Published:2009/7/15 4:53:00 Author:Jessie | From:SeekIC

Uses MC14021 8-bit shift register in conjunction with MC14507 EXCLUSIVE-OR gates to generate pseudorandom digital code. To develop code pattern, 1st, 6th, 7th, and 8th bits are sent through EXCLU-SIVE-OR gates and fed back to shift-register input. Output can be used as random test signal or for protecting messages sent over public channels or stored in public files. Digital message is scrambled by mixing it with output of code generator in EXCLUSIVE-OR gate. Functionally identical 255-bit random generator is used at receiver to unscramble data. Decoding circuit must have access to sending clock and means for synchronizing so as to put both registers into all-1 state. Register in receiver goes through all its states within 255 clock pulses; when it reaches all-1 state, signal is fed back to sender for releasing FF-1 so scrambling can commence. Article traces operation in detail. -J. Halligan, Pseudo-Random Number Generator Uses CMOS Logic, EDN Magazine, Aug. 15, 1972, p 42-43.



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