PLL_DIVIDER

Published:2009/7/6 3:11:00 Author:May | From:SeekIC

Simple phase-locked loop is suitable for generating integral submultiples M of input frequency. Values shown give M of 2.Square-wave input reference is limited in amplitude to supply voltage by first CMOS inverter A3A. RC network R9-C2, integrates output to give 2 V P-P triangle across C2 for sampling by sample-and-hold switch sections S1 and S2 of 4016 CMOS analog switch. Sampled error voltage of loop, stored on CH2, is read out by FET amplifier A2. Amplified error voltage is applied to A1 through R5 to induce changes in center frequency of A1 as required to maintain locked condition.-W. G. Jung, IC Timer Cookbook, Howard W. Sams, Indianapolis, IN, 1977, p 220-224.



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