MONOSTABLE_MVBR_DELAY

Published:2009/7/15 3:40:00 Author:Jessie | From:SeekIC

Prevents certain circuits from operating until proper time and generates and shapes required output pulses. Is triggered by positive pulse produced by input differentiating circuit. Circuits are cascaded, and second stage starts its delay coincident with trailing edge of first delay output pulse.-W. W. Grannemann et al, Pulse. Height-to-Digital Signal Converter, Electronics, 33:2, p 58-60.



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