KEYER_WITH_MEMORY

Published:2009/7/11 3:58:00 Author:May | From:SeekIC

Low-drain CMOS circuit permits storage in RAM of message being keyed, for repeated later use by pushing button.Includes monitor, simple weight control, and both positive and negative keying outputs. Playback of stored message can be interrupted by closing either paddle contact. 1024-bit memory will hold two runs of alphabet, two sets of numbers, and several punctuation marks. Dot is stored as 1 followed.by 0; dash is three is followed by 0, Free-running clock ensures that spaces will be recorded.-C. B. Opal, The Micro-TO MeGsage Keyer, QST, Feb. 1978, p 11-14.



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