HOUR_TIME_DELAY_SAMPLING_CIRCUIT

Published:2009/7/7 3:29:00 Author:May | From:SeekIC

The circuit lowers the effective peak current of the output PUT, Q2. By allowing the capacitor to charge with high gate voltage and periodically lowering gate voltage, when Q1 fires, the timing resistor can be a value which supplies a much lower current than Ip. The triggering requirement here is that minimum charge to trigger flow through the timing resistor during the period of the Q1 oscillator. This is not capacitor size dependent, only capacitor leakage and stability dependent.



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