FASTER_PHASE_LOCK

Published:2009/7/6 1:15:00 Author:May | From:SeekIC

Circuit was developed to reduce the normally long acquisition time of phase-locked loops when measuring frequency of short signal bursts. Synchronization of VCO to input phase allows correction pulses to be developed in correct polarity only, to give lockup time less than 10 cycles of input when using idling frequency of 12 kHz for VCO. Input signals are compared to those of VCO at EXCLUSIVE-OR gate A. Gating of error pulses by gate F and flip-flop G-H allows I or J to drive current pulses of correct polarity into C1. Voltage correction on C1, controlled by values of R2 and R3, is proportional to width of error pulses. Article covers circuit operation in detail.-R. Bohlken, A Synchronized Phase Locked Loop, EDN Magazine, March 20, 1973, p 84-85.



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