DIGITAL_LATCH_WITH_SAFETY_RESET_FEATURE

Published:2009/7/14 12:08:00 Author:May | From:SeekIC

The time diagram illustrates the various modes of operation of the circuit. A high S input causes the output (Q) to go low. Thereafter, a high R input can reset Q to high, but only so long as S remains low.The asynchronous digital latching circuit is designed for use in a safety-related application, like turning off power in response to an alarm signal. During normal operation in the absence of an alarm, the SET (S) and RESET input voltages are low or off, while the output voltage (Q) is high or on. The SET input constitutes the alarm signal: Whenever S goes high (on), Q goes low (off), and thereafter remains low, even when S goes low. Thus, for example, the circuit keeps a power supply turned off even when the alarm has been shut off. If a safe condition has been restored, then the circuit can be reset to Q high by applying a high (on) signal to the RESET ( R ) input terminal. However, regardless of the R input level, Q cannot be driven high as long as S remains high; that is, the circuit cannot be reset if the alarm signal is still on. Thus, the RESET signal cannot override the alarm signal and thereby provide a false indication of safety. Also, this does not go into oscillation when the SET and RESET inputs change simultaneously.



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Basic_Circuit/Digital_Circuit/DIGITAL_LATCH_WITH_SAFETY_RESET_FEATURE.html

Print this Page | Comments | Reading(3)