Published:2011/7/29 1:26:00 Author:Lucas | Keyword: 74 Series , digital circuit , 8-bit shift register | From:SeekIC
Parallel storage; right shift(direction is from the QA to QH): left shift(direction is from the QH to QA); it forbids the clock.
a. .. h= the input of steady-state input level of A to H.
QAo,QBo, QGo, QHo=the input of steady-state input level of QAo,QBo, QGo, QHo.
QAn, QBn= the corresponding level ofQA, QB before the next jump of the clock.
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