Published:2009/7/25 4:49:00 Author:Jessie | From:SeekIC
Figure 9-12 shows the ADC0816/17 connected to provide for an ADC with 16 differential inputs. This circuit is a modification of the circuit in Fig. 9-10. The CD4051 addressing is changed, and a differential amplifier is added between the multiplexer outputs and the comparator input. The select logic for the CD4051 is modified to enable the switches so that they can be selected in parallel with the ADC. The output of the three multiplexers are connected to a differential amplifier, composed of two inverting amplifiers with gain and offset trimmers. A dual op-amp configuration of inverting amplifiers can be trimmed easily, and has less-stringent feedback-resistor matching requirements (than a single op amp). The transfer equation for the dual op amp shown is:
The propagation delay through the op amps is an important consideration. There must be sufficient time between the analog switch-selection and start-conversion to allow the analog signal at the comparator input to settle. Using the LF353 op amp shown, the delay is about 5 pus. The op-amp gain and offset controls are adjusted to provide the zero and full-scale digital-output readings for the analog-in-put range or span. NATIONAL SEMICONDUCTOR, APPLICATION NOTE 258, P. 598.
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