D_BISTABLE

Published:2009/7/14 11:27:00 Author:May | From:SeekIC

The interesting point of this circuit is that a D-type bistable is used as an inverter. When the level at the input changes from high to low, the bistable is reset and its Q output goes high. When the input becomes low, the reset is removed and the Q output goes low. The delay introduced by network R1-C1 between the RESET input and the CLOCK input makes it possible to trigger the bistable at the leading edge of the input signal. As an example, in the case of a dual D-bistable Type 74HCT74, the time needed for a clock pulse to be accepted after the reset has been removed is 5 ns. Therefore, an RC introducing a delay of 7.5 ns gives a reasonable safety margin. The reduced edge gradient of the clock pulse does not create any problems because the maximum allowed rise time of the clock input is 500 ns. To obviate asymmetrical output signals, it is advisable to limit the input frequency to about 1 MHz with component values as specified.



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