Published:2009/7/10 5:18:00 Author:May | From:SeekIC
This circuit, instead of dividing by an integer, divides the input signal by N+1/2. With the feedback connections exactly as the figure shows, the circuit divides by 3.5. Point C ultimately controls when the input clocks the 74HC1614-bit counter. When C=0, the positive edge of the input triggers the counter. If C=1, the negative edge of the input triggers the counter. Each time that point C changes level, the circuit shortens the output pulse width of the counter by half of an input cycle. Thus, the counter's divisor depends on how many changes occur at point C during one output period.
Although the figure divides by 3.5, feeding back different counter outputs produces different divisors. Generally, an m-bit binary counter with pure exclusive-OR (XOR) feedback can form an N+1/2 counter, where N ranges from 2m-2+1/2 to 2m-1/2. The divided output is available at the m-1 bit of the counter.
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