DIVIDE_BY_5_WITH_TWO_GATES_AND_3_BITS

Published:2009/7/6 3:28:00 Author:May | From:SeekIC

Arrangement shown for dlviding clock inputfrequency by 5 requires onlytwo gates from 846 IC and 3 bits of 852 JK flip-flop storage to glve square-wave output pulses having 50% duty cycle．-C,L,Maginnlss, Another Reader Respondsto Odd Modulo Dlvider,EDN Magazine,Oct,15,1972,p 57.



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