DIVIDE_BY_15

Published:2009/7/6 3:17:00 Author:May | From:SeekIC

Input clock is altemately inverted and noninverted by gates operating in coniunction with 4 bits of storage using 852 JK flip-flops, to give square-wave output at 1/15 of clock frequency.-C. W. Hardy, Reader Responds to Odd Modulo Divider in July 1st EDN, EDN Magazine, Oct, 1, 1972, p 50.



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