DIGITAL_RAMP

Published:2009/7/14 0:33:00 Author:May | From:SeekIC

Digiial-to-analog technique using single CD4024A CMOS shift register eliminates temperature and linearity problems normally encountered when using RC circuit to drive VCO of digital ramp. Ramp is generated from 50-kHz clock and stopped by applying reset pulse to counters, Use of stable but variable supply for IC permits adjustment of ramp output amplitude, Ramp itself consists of large number of small steps; if these steps are too large, second CD4024A can be added and clock frequency increased. If response of 741 opamp is not adequate for very steep ramps, use opamp having higher slew rate.-K. Bower, CMOS Linear-Ramp Generator Has Amplitude Control, EDN Magazine, June 20, 1973, p 87.



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