DIGITAL_FREQUENCY_DOUBLER_CIRCUIT

Published:2009/7/12 23:51:00 Author:May | From:SeekIC

The 74LS393 is designed to advance one count on the positive-to-negative transition of the pulse at the clock input (pins 1 and 13). An inverter in front of the B section of the counter causes the B section to advance one count on the negative-to-positive transition of the input pulse. Each section of the counter is cleared with a positive-going pulse on the master reset input (pins 2 and 12). Positive-going output pulses from pins 6 and 10 of IC2 reset the respective counters. The duration of the pulses depends upon the propagation delay of the inverters. With the 74LS04 hex inverter, delay will probably be in the vicinity of 20 to 25 ns. The output pulses are also connected to the remaining inverter gate through switching diodes and a pull-down resistor, which configures the remaining inverter as a NOR gate. The output at pin 8 of IC2 represents the input frequency multiplied by 2.



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