Published:2009/6/24 5:25:00 Author:May | From:SeekIC
This circuit uses a symmetrical limiter obtained by biasing a transistor to a Q point that is half of the supply voltage and driving it into saturation and cutoff. An input of 1 to 2 V RMS is sufficient. This output will be approximately 4Vp-p into a high-impedance load.
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