SAMPLING_RATE_PHASE_LOCK

Published:2009/6/23 2:44:00 Author:May | From:SeekIC

Most digital scopes have record lengths that are power of 2 (e.g., 1024 points) and sampling rates constrained to a 1-2-5 sequence. This can lead to measurement errors on power-line waveforms because an integral number of line cycles can't be captured. Digital scopes that calculate measurements, such as the rms level, across the entire record will be in error.One solution to this problem is to phase-lock the scope's sampling rate to the line frequency by exploiting the external clock input found on some digital scopes. Phase-locking the sampling to line frequency also tracks variations in the power-line frequency.A 9- or 12-Vac wall transformer provides the circuit's power and the frequency reference. The negative output of the diode bridge refines the circuit ground. The 78L05 regulator provides the +5 V supply for the three ICs. R3 and C2 create a low-pass filter on the half-cycles from one of the floating transformer outputs. R3 also limits the current into the internal diode clamps of the inverter gate.The inverter output becomes the power-line frequency reference and is one input (SIG in to the phase comparator) of the Signetics 74HC4046A phase-locked loop (PLL). The 74HC4040 divides the PLL output frequency by 1024 and feeds the divided clock back to the other PLL phase-comparator input (COMP in). The phase-comparator output (PC2) is filtered and drives the PLL's control voltage (VCO in) so that the output frequency is 1024 times the reference frequency.With the loop filter shown, the output frequency locks to the line frequency in about 10 s. The oscillator is locked to both 50- and 60-Hz inputs using a 74HC4046A and the values shown for resis-tors RI and R2 and capacitor C1.The output signal is buffered and sent to the scope's external clock input, which is typically a TTL-compatible input. A different tap from the 74HC4040 can be selected to control the number or cycles captured in one scope record.



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