ADC_CONTROLLING_DIGITAL_POTENTIOMETER

Published:2009/7/13 3:09:00 Author:May | From:SeekIC

This design was created to control a DS1267 digital potentiometer with an analog signal. The DS1267 is a dual-pot chip, but this design will enable control of only one section. Here, the analog-to-digital converter (ADC) used is an ADC0833 8-bit serial I/O converter with a four-channel multi-plexer. The analog input to channel 3 of the ADC is employed. The timing diagram illustrates the operation of the circuit. A negative start pulse on the chip select of the ADC starts the sequence (the pulse must stay low for at least 14 clock pulses or until the ADC's SAR Status line comes high). The next five clock pulses perform various housekeeping in the ADC, The Data 0ut line comes out of tristate on the negative edge of the fifth pulse, and the SAR Status line comes high to signal a conversion in progress. The first bit on the Data Out line is a leading zero for one clock period. Data is clocked into the DS1267 on the positive edge of the clock pulse. The input format for the DS1267 requires that the first bit determine the stack select (used in the DS1267 when the two pots are com-bined) and the following 8 bits provide data. Following transmission of these 9 bits, the SAR Status line goes high, disabling further input to the DSl267 (the ADC0833's output format continues trans-mission of 8 more bits of the conversion in reverse order, but the DS1267 ignores these). Input range for the ADC is 0 to 5 V. Pin 1 of the DS1267 is shown tied to ground (for pot connections referenced to ground; however, -SVcan be used to provide a range of 15 to -5 V on the pot).



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