74 series digital circuit of 7497 synchronous 6 binary coefficient multiplier

Published:2011/4/2 3:58:00 Author:Ecco | Keyword: digital circuit , synchronous 6 , binary coefficient, multiplier | From:SeekIC

Executive fixed coefficient or variable coefficient fractional frequency: typical highest clock frequency 32MHz; When clearing, choose input for low level, counter begins the work, the output frequency equals to input frequency multiplied by input coefficient divided by 64. H is high level, L is low level, X is uncertain, others are digital reading. 1. This is a simple chart to show the clearing function. The state of clock and strobe will make an influence on the logic level of Y and Z. For example, the unit /cascade is in low level, the output will keep high level. 2. The coefficient in input terminal is constant or variable coefficient input. 3. The unit/cascade is not allow to output Y.



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