Published:2011/6/13 20:38:00 Author:Borg | Keyword: synchronized signal generator | From:SeekIC
See as the figure, no matter what polarity of the input signal is, the circuit can generate a passive synchronized pulse. The 5v voltage which is imposed on R1 and R2 is split into two 2.5V voltages, so that we don't needed to magnify the input signal. The RC net of R3C1, which is on a OR gate terminal, can keep 2-pin in a high LEV when there is an external passive synchronized pulse, because the passive synchronized pulse is very narrow, which makes the capacitor C2 charges under the limited voltage; therefore, the pulse is no inverted. The a positive pulse is input, the LEV of 2-pin is not allowed to be raised, so the input is inverted.
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