Published:2011/7/21 9:08:00 Author:Joyce | Keyword: Silicon Controlled, Trigger | From:SeekIC
As shown in the figure, 555, R1, RP1, C2 and some other components constitute the trigger delay circuit. Commonly, 555 is in the state of reset , and feet 3 displays a low level since R1 is connected with VDD; When triggered signals come in , SCR will break over ,feet 2 will have a low level signal which will turn 555 to output a high level. The temporary stable width is: τ = 1.1 RP1C2 . After triggering, SCR will shut off. This circuit can lower the requirement of triggering pulse. If CMOS type 555 (or 556) is used, the triggering current can also be reduced.
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