SYNCHRONOUS_SAMPLER

Published:2009/7/23 22:00:00 Author:Jessie | From:SeekIC

Time jitter of digital receiver output pulse is eliminated by synchronous sampling of detected signal. Each bit is sampled by local clock pulses that trigger flip-flop Q1-Q2. Two outputs of slicer, 180° out of phase, are applied to bases of Q1 and Q2. Output of flip-lop is regenerated information, free of jitter.-J. L. Hollis, Sending Digital Data Over Narrow. Band Lines, Electronics, 32:23, p 72-74.



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